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CYDM064B16, CYDM128B16, CYDM256B16 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL(R)
Dual-Port Static RAM
Features

True dual-ported memory cells that allow simultaneous access of the same memory location 4, 8, or 16K x 16 organization Ultra Low operating power Active: ICC = 15 mA (typical) at 55 ns Standby: ISB3 = 2 A (typical) Small footprint: Available in a 6x6 mm 100-pin Pb-free vfBGA Port independent 1.8V, 2.5V, and 3.0V IOs Full asynchronous operation Automatic power down Pin select for Master or Slave

Expandable data bus to 32 bits with Master or Slave chip select when using more than one device On-chip arbitration logic Semaphores included to permit software handshaking between ports Input read registers and output drive registers INT flag for port-to-port communication Separate upper-byte and lower-byte control Industrial temperature ranges

Selection Guide for VCC = 1.8V
Parameter Port IO Voltages (P1-P2) Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 Typical Standby Current for ISB3 CYDM256B16, CYDM128B16, CYDM064B16 (-55) 1.8V -1.8V 55 15 2 2 Unit V ns mA A A
Selection Guide for VCC = 2.5V
Parameter Port IO Voltages (P1-P2) Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 Typical Standby Current for ISB3 CYDM256B16, CYDM128B16, CYDM064B16 (-55) 2.5V-2.5V 55 28 6 4 Unit V ns mA A A
Selection Guide for VCC = 3.0V
Parameter Port IO Voltages (P1-P2) Maximum Access Time Typical Operating Current Typical Standby Current for ISB1 Typical Standby Current for ISB3 CYDM256B16, CYDM128B16, CYDM064B16 (-55) 3.0V-3.0V 55 42 7 6 Unit V ns mA A A
Cypress Semiconductor Corporation Document #: 001-00217 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709
* 408-943-2600 Revised July 31, 2008
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CYDM064B16, CYDM128B16, CYDM256B16
Logic Block Diagram [1, 2]
IO[15:0]L UBL LBL IO Control
IO[15:0]R UBR IO Control LBR
16K X 16 Dual Ported Array
Address Decode
Address Decode
A[13:0]L CE L OE L R/W L SEML BUSY L Interrupt Arbitration Semaphore
A [13:0]R CE R OE R R/W R SEMR BUSY R
INTL
Mailboxes
INTR
M/S
CEL OEL R/WL IRR0 ,IRR1
Input Read Register and Output Drive Register
CE R OE R R/W R ODR0 - ODR4
SFEN
Notes 1. A0-A11 for 4K devices; A0-A12 for 8K devices; A0-A13 for 16K devices. 2. BUSY is an output in master mode and an input in slave mode.
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CYDM064B16, CYDM128B16, CYDM256B16
Pinouts
Figure 1. Ball Diagram - 100-Ball 0.5 mm Pitch BGA (Top View) [3, 4, 5, 6, 7] CYDM064B16, CYDM128B16, CYDM256B16 1 A B C D E F G H J K A5R A3R A0R 2 A8R A4R A1R 3 A11R A7R A2R 4 UBR A9R A6R 5 VSS CER LBR A10R VSS VCC OEL CEL VCC SEML 5 6 SEMR R/WR 7 IO15R OER 8 IO12R VDDIOR IO11R IO8R VDDIOR IO0R IO12L 9 IO10R IO9R IO7R IO5R IO1R 10 VSS IO6R VSS IO2R VSS A B C D E F G H J K
IRR1[6] IO14R A12R[3] IO13R VSS VSS IO3L IO1L VSS R/WL 6 IO4R IO3R IO11L
ODR4 ODR2 BUSYR INTR VSS M/S ODR3 INTL A1L A12L[3] LBL IRR0[5] UBL 4
SFEN ODR1 BUSYL ODR0 A0L A3L A6L 1 A2L A4L A7L A8L 2 A5L A9L A10L A11L 3
IO15L VDDIOL IO14L NC[7] IO8L IO5L 9 IO13L IO10L IO9L IO7L 10
VDDIOL NC[7] IO4L IO0L 7 IO6L IO2L 8
Notes 3. A12L and A12R are NC pins for CYDM064B16. 4. IRR functionality is not supported for the CYDM256B16 device. 5. This pin is A13L for CYDM256B16 device. 6. This pin is A13R for CYDM256B16 device. 7. Leave this pin unconnected. No trace or power component can be connected to this pin.
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CYDM064B16, CYDM128B16, CYDM256B16
Table 1. Pin Definitions - 100-Ball 0.5 mm Pitch BGA (CYDM064B16, CYDM128B16, CYDM256B16) Left Port CEL R/WL OEL A0L-A13L IO0L-IO15L SEML UBL LBL INTL BUSYL Right Port CER R/WR OER A0R-A13R IO0R-IO15R SEMR UBR LBR INTR BUSYR IRR0, IRR1 ODR0-ODR4 SFEN M/S VCC GND VDDIOL VDDIOR NC Chip Enable Read or Write Enable Output Enable Address (A0-A11 for 4K devices; A0-A12 for 8K devices; A0-A13 for 16K devices) Data Bus Input or Output for x16 devices Semaphore Enable Upper Byte Select (IO8-IO15) Lower Byte Select (IO0-IO7) Interrupt Flag Busy Flag Input Read Register for CYDM064B16 and CYDM128B16 A13L and A13R for CYDM256B16. Output Drive Register. These outputs are Open Drain. Special Function Enable Master or Slave Select Core Power Ground Left Port IO Voltage Right Port IO Voltage No Connect. Leave this pin Unconnected. Description
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CYDM064B16, CYDM128B16, CYDM256B16
Functional Description
The CYDM256B16, CYDM128B16, and CYDM064B16 are low power CMOS 4K, 8K,16K x 16 dual-port static RAMs. Arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided that permit independent, asynchronous access for reads and writes to any location in memory. The devices can be used as standalone 16-bit dual-port static RAMs or multiple devices can be combined to function as a 32-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor or multiprocessor designs, communications status buffering, and dual-port video or graphics memory. Each port has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY indicates that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT) permits communication between ports or systems through a mail box. The semaphores are used to pass a flag or token, from one port to the other, to indicate that a shared resource is in use. The semaphore logic consists of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power down feature is controlled independently on each port by a Chip Enable (CE) pin. The CYDM256B16, CYDM128B16, CYDM064B16 are available in 100-ball 0.5 mm pitch Ball Grid Array (BGA) packages.
Read Operation
When reading the device, the user must assert both the OE and CE pins. Data is available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted.
Interrupts
The upper two memory locations may be used for message passing. The highest memory location (FFF for the CYDM064B16, 1FFF for the CYDM128B16, 3FFF for the CYDM256B16) is the mailbox for the right port and the second-highest memory location (FFE for the CYDM064B16, 1FFE for the CYDM128B16, 3FFE for the CYDM256B16) is the mailbox for the left port. When one port writes to the other port's mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user-defined. Each port can read the other port's mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor's interrupt request input pin. On power up, an initialization program must be run and the interrupts for both ports must be read to reset them. The operation of the interrupts and their interaction with Busy are summarized in Table 3 on page 7.
Busy
The CYDM256B16, CYDM128B16, and CYDM064B16 provide on-chip arbitration to resolve simultaneous memory location access (contention). If both port CEs are asserted and an address match occurs within tPS of each other, the busy logic determines which port has access. If tPS is violated, one port definitely gains permission to the location. However, which port gets this permission cannot be predicted. BUSY is asserted tBLA after an address match or tBLC after CE is taken LOW.
Power Supply
The core voltage (VCC) can be 1.8V, 2.5V, or 3.0V, as long as it is lower than or equal to the IO voltage. Each port can operate on independent IO voltages. This is determined by what is connected to the VDDIOL and VDDIOR pins. The supported IO standards are 1.8V or 2.5V LVCMOS and 3.0V LVTTL.
Write Operation
Data must be set up for a duration of tSD before the rising edge of R/W to guarantee a valid write. A write operation is controlled by either the R/W pin (see Figure 5 on page 18) or the CE pin (see Figure 6 on page 18). Required inputs for noncontention operations are summarized in Table 2 on page 7. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output. Otherwise, the data read is not deterministic. Data is valid on the port tDDD after the data is presented on the other port.
Master/Slave
An M/S pin is provided to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This allows the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA). Otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, as a result, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave.
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CYDM064B16, CYDM128B16, CYDM256B16
Input Read Register
The Input Read Register (IRR) captures the status of two external input devices that are connected to the Input Read pins. The contents of the IRR read from address x0000 from either port. During reads from the IRR, DQ0 and DQ1 are valid bits and DQ<15:2> are don't care. Writes to address x0000 are not allowed from either port. Address x0000 is not available for standard memory accesses when SFEN = VIL. When SFEN = VIH, address x0000 is available for memory accesses. The inputs are 1.8V/2.5V LVCMOS or 3.0V LVTTL, depending on the core voltage supply (VCC). Refer to Table 4 on page 8 for Input Read Register operation. IRR is not available in the CYDM256B16, because the IRR pins are used as extra address pins A13L and A13R.
Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0-2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only IO0 is used. If a zero is written to the left port of an available semaphore, a one appears at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore is set to one for both sides. However, if the right port requests the semaphore (written a zero) while the left port has control, the right port immediately owns the semaphore as soon as the left port releases it. Table 6 on page 8 shows sample semaphore operations. When reading a semaphore, all sixteen data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore is definitely obtained by one side or the other, but there is no guarantee which side controls the semaphore. On power up, both ports must write "1" to all eight semaphores.
Output Drive Register
The Output Drive Register (ODR) determines the state of up to five external binary state devices by providing a path to VSS for the external circuit. These outputs are Open Drain. The five external devices can operate at different voltages (1.5V VDDIO 3.5V) but the combined current cannot exceed 40 mA (8 mA max for each external device). The status of the ODR bits are set using standard write accesses from either port to address x0001 with a "1" corresponding to on and "0" corresponding to off. The status of the ODR bits can be read with a standard read access to address x0001. When SFEN = VIL, the ODR is active and address x0001 is not available for memory accesses. When SFEN = VIH, the ODR is inactive and address x0001 can be used for standard accesses. During reads and writes to ODR DQ<4:0> are valid and DQ<15:5> are don't care. Refer to Table 5 on page 8 for Output Drive Register operation.
Architecture
The CYDM256B16, CYDM128B16, and CYDM064B16 consist of an array of 4K, 8K, or 16K words of 16 dual-port RAM cells, IO and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes or reads to the same location, a BUSY pin is provided on each port. Two Interrupt (INT) pins can be used for port-to-port communication. Two Semaphore (SEM) control pins are used to allocate shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device.
Semaphore Operation
The CYDM256B16, CYDM128B16, and CYDM064B16 provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value is available tSWRD + tDOE after the rising edge of the semaphore write. If the left port is successful (reads a zero), it assumes control of the shared resource. Otherwise (reads a one), it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side succeeds in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request.
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CYDM064B16, CYDM128B16, CYDM256B16
Table 2. NonContending Read/Write Inputs CE H X L L L L L L X H X H X L L X X R/W X X L L L H H H X H H OE X X X X X L L L H L L X X X X UB X H L H L L H L X X H X H L X LB X H H L L H L L X X H X H X L SEM H H H H H H H H X L L L L L L Outputs IO8-IO15 High Z High Z Data In High Z Data In Data Out High Z Data Out High Z Data Out Data Out Data In Data In IO0-IO7 High Z High Z High Z Data In Data In High Z Data Out Data Out High Z Data Out Data Out Data In Data In Operation Deselected: Power down Deselected: Power down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled Read Data in Semaphore Flag Read Data in Semaphore Flag Write DIN0 into Semaphore Flag Write DIN0 into Semaphore Flag Not Allowed Not Allowed
Table 3. Interrupt Operation Example (Assumes BUSYL = BUSYR = HIGH)[8] Left Port Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag R/WL L X X X CEL L X X L OEL X X X L A0L-13L 3FFF[11] X X 3FFE[11] INTL X X L[9] H[10] R/WR X X L X CER X L L X Right Port OER X L X X A0R-13R X 3FFF[11] 3FFE[11] X INTR L[10] H[9] X X
Notes 8. See Interrupts Functional Description for specific highest memory locations by device. 9. If BUSYR = L, then no change. 10. If BUSYL = L, then no change. 11. See section Functional Description on page 5 for specific addresses by device.
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CYDM064B16, CYDM128B16, CYDM256B16
Table 4. Input Read Register Operation[12, 15] SFEN H L CE L L R/W H H OE L L UB L X LB L L ADDR IO0-IO1
[13] [14]
IO2-IO15 VALID X
[13]
Mode Standard Memory Access IRR Read
x0000-Max VALID x0000
VALID
Table 5. Output Drive Register [16] SFEN H L L CE L L L R/W H L H OE X[17] X L UB L[13] X X LB L[13] L L ADDR IO0-IO4 VALID[14] VALID[14] IO5-IO15 X X Mode ODR Write[16, 18] ODR Read[16]
x0000-Max VALID[13] VALID[13] Standard Memory Access x0001 x0001
Table 6. Semaphore Operation Example Function No action Left port writes 0 to semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore IO0-IO15 Left 1 0 0 1 1 0 1 1 1 0 1 IO0-IO15 Right 1 1 1 0 0 1 1 0 1 1 1 Semaphore free Left Port has semaphore token No change. Right side has no write access to semaphore. Right port obtains semaphore token No change. Left port has no write access to semaphore. Left port obtains semaphore token Semaphore free Right port has semaphore token Semaphore free Left port has semaphore token Semaphore free Status
Notes 12. SFEN = VIL for IRR reads 13. UB or LB = VIL. If LB = VIL, then DQ<7:0> are valid. If UB = VIL then DQ<15:8> are valid. 14. LB must be active (LB = VIL) for these bits to be valid. 15. SFEN active when either CEL = VIL or CER = VIL. It is inactive when CEL = CER = VIH. 16. SFEN = VIL for ODR reads and writes. 17. Output enable must be low (OE = VIL) during reads for valid data to be output. 18. During ODR writes data are also written to the memory.
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CYDM064B16, CYDM128B16, CYDM256B16
Maximum Ratings
Exceeding maximum ratings[19] may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +3.3V DC Voltage Applied to Outputs in High-Z State.......................... -0.5V to VCC + 0.5V DC Input Voltage[20] ...............................-0.5V to VCC + 0.5V Output Current into Outputs (LOW) .............................90 mA
Static Discharge Voltage .......................................... > 2000V Latch-up Current ................................................... > 200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC 1.8V 100 mV 2.5V 100 mV 3.0V 300 mV 1.8V 100 mV 2.5V 100 mV 3.0V 300 mV
Industrial
-40C to +85C
Electrical Characteristics for VCC = 1.8V
Over the Operating Range CYDM256B16, CYDM128B16, CYDM064B16 Parameter VOH Description P1 IO Voltage P2 IO Voltage Output HIGH Voltage (IOH = -100 A) Output HIGH Voltage (IOH = -2 mA) Output HIGH Voltage (IOH = -2 mA) VOL Output LOW Voltage (IOL = 100 A) Output HIGH Voltage (IOL = 2 mA) Output HIGH Voltage (IOL = 2 mA) VOL ODR ODR Output LOW Voltage (IOL = 8 mA) 1.8V (any port) 2.5V (any port) 3.0V (any port) 1.8V (any port) 2.5V (any port) 3.0V (any port) 1.8V (any port) 2.5V (any port) 3.0V (any port) VIH Input HIGH Voltage 1.8V (any port) 2.5V (any port) 3.0V (any port) VIL Input LOW Voltage 1.8V (any port) 2.5V (any port) 3.0V (any port) IOZ Output Leakage Current 1.8V 2.5V 3.0V ICEX ODR ODR Output Leakage Current. VOUT = VDDIO 1.8V 2.5V 3.0V IIX Input Leakage Current 1.8V 2.5V 3.0V
Notes 19. The voltage on any input or IO pin can not exceed the power pin during power up. 20. Pulse width < 20 ns.
-55 Min VDDIO - 0.2 2.0 2.1 0.2 0.4 0.4 0.2 0.2 0.2 1.2 1.7 2.0 -0.2 -0.3 -0.2 -1 -1 -1 -1 -1 -1 -1 -1 -1 VDDIO + 0.2 VDDIO + 0.3 VDDIO + 0.2 0.4 0.6 0.7 1 1 1 1 1 1 1 1 1 Typ. Max
Unit V V V V V V V V V V V V V V V A A A A A A A A A
1.8V 2.5V 3.0V 1.8V 2.5V 3.0V 1.8V 2.5V 3.0V
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CYDM064B16, CYDM128B16, CYDM256B16
Electrical Characteristics for VCC = 1.8V
Over the Operating Range
(continued) CYDM256B16, CYDM128B16, CYDM064B16
Parameter ICC ISB1
Description P1 IO Voltage P2 IO Voltage Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Ind. 1.8V 1.8V 1.8V 1.8V
-55 Min Typ. 15 2 Max 25 6
Unit mA A
Standby Current (Both Ports TTL Ind. Level) CEL and CER VCC - 0.2, SEML = SEMR = VCC - 0.2, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Ind.
ISB2 ISB3
1.8V 1.8V
1.8V 1.8V
8.5 2
14 6
mA A
Standby Current (Both Ports CMOS Ind. Level) CEL and CER VCC - 0.2V, SEML and SEMR > VCC - 0.2V, f = 0 Standby Current (One Port CMOS Ind. Level) CEL | CER VIH, f = fMAX[21]
ISB4
1.8V
1.8V
8.5
14
mA
Electrical Characteristics for VCC = 2.5V
Over the Operating Range CYDM256B16, CYDM128B16, CYDM064B16 Parameter VOH VOL VOL ODR VIH VIL IOZ ICEX ODR IIX ICC Description P1 IO Voltage P2 IO Voltage Output HIGH Voltage (IOH = -2 mA) Output LOW Voltage (IOL = 2 mA) ODR Output LOW Voltage (IOL = 8 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current ODR Output Leakage Current. VOUT = VCC Input Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Ind. 2.5V (any port) 3.0V (any port) 2.5V (any port) 3.0V (any port) 2.5V (any port) 3.0V (any port) 2.5V (any port) 3.0V (any port) 2.5V (any port) 3.0V (any port) 2.5V 3.0V 2.5V 3.0V 2.5V 3.0V 2.5V 2.5V 3.0V 2.5V 3.0V 2.5V 3.0V 2.5V 1.7 2.0 -0.3 -0.2 -1 -1 -1 -1 -1 -1 28 -55 Min 2.0 2.1 0.4 0.4 0.2 0.2 VDDIO + 0.3 VDDIO + 0.2 0.6 0.7 1 1 1 1 1 1 40 Typ. Max V V V V V V V V V V A A A A A A mA Unit
Notes 21. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.
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CYDM064B16, CYDM128B16, CYDM256B16
Electrical Characteristics for VCC = 2.5V
Over the Operating Range
(continued) CYDM256B16, CYDM128B16, CYDM064B16
Parameter ISB1
Description P1 IO Voltage P2 IO Voltage Standby Current (Both Ports TTL Ind. Level) CEL and CER VCC - 0.2, SEML= SEMR = VCC - 0.2, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Ind. 2.5V 2.5V
-55 Min Typ. 6 Max 8
Unit A
ISB2 ISB3
2.5V 2.5V
2.5V 2.5V
18 4
25 6
mA A
Standby Current (Both Ports CMOS Ind. Level) CEL and CER VCC - 0.2V, SEML and SEMR > VCC - 0.2V, f = 0 Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX[21] Ind.
ISB4
2.5V
2.5V
18
25
mA
Electrical Characteristics for 3.0V Over the Operating Range
CYDM256B16, CYDM128B16, CYDM064B16 Parameter VOH VOL VOL ODR VIH VIL IOZ ICEX ODR IIX ICC ISB1 Description P1 IO Voltage P2 IO Voltage Output HIGH Voltage (IOH = -2 mA) Output LOW Voltage (IOL = 2 mA) ODR Output LOW Voltage (IOL = 8 mA) Input HIGH Voltage Input LOW Voltage Output Leakage Current ODR Output Leakage Current. VOUT = VCC Input Leakage Current Operating Current (VCC = Max., IOUT = 0 mA) Outputs Disabled Ind. 3.0V (any port) 3.0V (any port) 3.0V (any port) 3.0V (any port) 3.0V (any port) 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 3.0V 2.0 -0.2 -1 -1 -1 42 7 -55 Min 2.1 0.4 0.2 VDDIO + 0.2 0.7 1 1 1 60 10 Typ. Max V V V V V A A A mA A Unit
Standby Current (Both Ports TTL Ind. Level) CEL and CER VCC - 0.2, SEML = SEMR = VCC - 0.2, f = fMAX Standby Current (One Port TTL Level) CEL | CER VIH, f = fMAX Ind.
ISB2 ISB3
3.0V 3.0V
3.0V 3.0V
25 6
35 8
mA A
Standby Current (Both Ports CMOS Ind. Level) CEL and CER VCC - 0.2V, SEML and SEMR > VCC - 0.2V, f = 0 Standby Current (One Port CMOS Level) CEL | CER VIH, f = fMAX[21] Ind.
ISB4
3.0V
3.0V
25
35
mA
Capacitance[22]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.0V Max 9 10 Unit pF pF
Note 22. Tested initially and after any design or process changes that may affect these parameters.
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CYDM064B16, CYDM128B16, CYDM256B16
AC Test Loads and Waveforms
3.0V/2.5V/1.8V 3.0V/2.5V/1.8V R1 OUTPUT C = 30 pF R2 VTH = 0.8V OUTPUT C = 30 pF RTH = 6 k R1 OUTPUT C = 5 pF R2
(a) Normal Load 3.0V/2.5V R1 R2 1022 792 1.8V 13500 10800
1.8V GND
(b) Thevenin Equivalent (Load 1) ALL INPUT PULSES
90% 10% 3 ns
(c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, and tLZWE including scope and jig)
10% 3 ns
90%
Switching Characteristics for VCC = 1.8V
Over the Operating Range[23] CYDM256B16, CYDM128B16, CYDM064B16 Parameter Read Cycle tRC tAA tOHA tACE[24] tDOE tLZOE
[25, 26, 27]
Description Min Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power up CE HIGH to Power down Byte Enable Access Time 0 5 5 5 55
-55 Max
Unit
ns 55 55 30 ns ns ns ns ns 25 ns ns 25 ns ns 55 55 ns ns
tHZOE[25, 26, 27] tLZCE[25, 26, 27] tHZCE[25, 26, 27] tPU[27] tPD[27] tABE[24]
Notes 23. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOI/IOH and 30 pF load capacitance. 24. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 25. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 26. Test conditions used are Load 3. 27. This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for VCC = 1.8V
Over the Operating Range[23]
(continued) CYDM256B16, CYDM128B16, CYDM064B16
Parameter Write Cycle tWC tSCE[24] tAW tHA tSA[24] tPWE tSD tHD tHZWE[26, 27] tLZWE[26, 27] tWDD[28] tDDD[28] Busy Timing tBLA tBHA tBLC tBHC tPS[30] tWB tWH tBDD[31] Interrupt Timing tINS tINR Semaphore Timing tSOP tSWRD tSPS tSAA
[29] [29]
Description Min Write Cycle Time CE LOW to Write End Address Valid to Write End Address Hold From Write End Address Setup to Write Start Write Pulse Width Data Setup to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid 0 55 45 45 0 0 40 30 0
-55 Max
Unit
ns ns ns ns ns ns ns ns 25 ns ns 80 80 ns ns
BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Setup for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid 5 0 35
45 45 45 45
ns ns ns ns ns ns ns
40
ns
INT Set Time INT Reset Time SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time 15 10 10
45 45
ns ns ns ns ns
55
ns
Notes 28. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 29. Test conditions used are Load 2. 30. Add 2ns to this parameter if VCC and VDDIOR are <1.8V, and VDDIOL is >2.5V at temperature <0C. 31. tBDD is a calculated parameter and is the greater of tWDD - tPWE (actual) or tDDD - tSD (actual).
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for VCC = 2.5V
Over the Operating Range CYDM256B16, CYDM128B16, CYDM064B16 Parameter Read Cycle tRC tAA tOHA tACE[24] tDOE tLZOE
[25, 26, 27]
Description Min Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power up CE HIGH to Power down Byte Enable Access Time 0 2 2 5 55
-55 Max
Unit
ns 55 55 30 ns ns ns ns ns 25 ns ns 25 ns ns 55 55 ns ns
tHZOE[25, 26, 27] tLZCE[25, 26, 27] tHZCE[25, 26, 27] tPU[27] tPD[27] tABE[24] Write Cycle tWC tSCE[24] tAW tHA tSA[24] tPWE tSD tHD tHZWE[26, 27] tLZWE[26, 27] tWDD[28] tDDD[28] Busy Timing tBLA tBHA tBLC tBHC tPS[30] tWB tWH tBDD[31]
[29]
Write Cycle Time CE LOW to Write End Address Valid to Write End Address Hold From Write End Address Setup to Write Start Write Pulse Width Data Setup to Write End Data Hold From Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid
55 45 45 0 0 40 30 0 25 0 80 80
ns ns ns ns ns ns ns ns ns ns ns ns
BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Setup for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid 5 0 35
45 45 45 45
ns ns ns ns ns ns ns
40
ns
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for VCC = 2.5V
Over the Operating Range
(continued) CYDM256B16, CYDM128B16, CYDM064B16
Parameter Timing[29] INT Set Time INT Reset Time
Description Min
-55 Max
Unit
Interrupt tINS tINR
45 45 15 10 10 55
ns ns ns ns ns ns
Semaphore Timing tSOP tSWRD tSPS tSAA SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time
Switching Characteristics for VCC = 3.0V
Over the Operating Range CYDM256B16, CYDM128B16, CYDM064B16 Parameter Read Cycle tRC tAA tOHA tACE[24] tDOE tLZOE
[25, 26, 27]
Description Min Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power up CE HIGH to Power down Byte Enable Access Time 0 1 1 5 55
-55 Max
Unit
ns 55 55 30 ns ns ns ns ns 25 ns ns 25 ns ns 55 55 ns ns
tHZOE[25, 26, 27] tLZCE[25, 26, 27] tHZCE[25, 26, 27] tPU[27] tPD[27] tABE[24] Write Cycle tWC tSCE[24] tAW tHA tSA[24] tPWE tSD tHD
Write Cycle Time CE LOW to Write End Address Valid to Write End Address Hold From Write End Address Setup to Write Start Write Pulse Width Data Setup to Write End Data Hold From Write End
55 45 45 0 0 40 30 0
ns ns ns ns ns ns ns ns
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Characteristics for VCC = 3.0V
Over the Operating Range
(continued) CYDM256B16, CYDM128B16, CYDM064B16
Parameter tHZWE[26, 27] tLZWE[26, 27] tWDD[28] tDDD[28] Busy tBLA tBHA tBLC tBHC tPS[30] tWB tWH tBDD[31] Interrupt tINS tINR Semaphore Timing tSOP tSWRD tSPS tSAA Timing[29] INT Set Time INT Reset Time Timing[29]
Description Min R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid 0
-55 Max 25
Unit ns ns 80 80 ns ns
BUSY LOW from Address Match BUSY HIGH from Address Mismatch BUSY LOW from CE LOW BUSY HIGH from CE HIGH Port Setup for Priority R/W HIGH after BUSY (Slave) R/W HIGH after BUSY HIGH (Slave) BUSY HIGH to Data Valid 5 0 35
45 45 45 45
ns ns ns ns ns ns ns
40
ns
45 45 15 10 10 55
ns ns ns ns ns ns
SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window SEM Address Access Time
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms
Figure 2. Read Cycle No.1 (Either Port Address Access) [32, 33, 34]
tRC ADDRESS tOHA DATA OUT tAA DATA VALID tOHA
PREVIOUS DATA VALID
Figure 3. Read Cycle No.2 (Either Port CE/OE Access) [32, 35, 36]
tACE tHZCE tDOE tHZOE tLZOE DATA OUT tLZCE tPU ICC CURRENT ISB tPD DATA VALID
CE and LB or UB OE
Figure 4. Read Cycle No. 3 (Either Port) [32, 34, 37, 38]
tRC ADDRESS tAA UB or LB tHZCE tLZCE tABE CE tACE tLZCE DATA OUT tHZCE tOHA
Notes 32. R/W is HIGH for read cycles. 33. Device is continuously selected CE = VIL and UB or LB = VIL. This waveform cannot be used for semaphore reads. 34. OE = VIL. 35. Address valid before or coincident with CE transition LOW. 36. To access RAM, CE = VIL, UB or LB = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. 37. R/W must be HIGH during all address transitions. 38. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM and a LOW UB or LB.
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 5. Write Cycle No.1: R/W Controlled Timing [37, 38, 39, 40, 41, 42]
tWC ADDRESS tHZOE [43] OE tAW CE
[41, 42]
tSA R/W tHZWE[43] DATA OUT NOTE 44
tPWE[40]
tHA
tLZWE NOTE 44 tSD tHD
DATA IN
Figure 6. Write Cycle No. 2: CE Controlled Timing [37, 38, 39, 44]
tWC ADDRESS tAW CE
[41, 42]
tSA R/W
tSCE
tHA
tSD DATA IN
tHD
Notes 39. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 40. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the IO drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 41. To access RAM, CE = VIL, SEM = VIH. 42. To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH. 43. Transition is measured 0 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested. 44. During this period, the IO pins are in the output state, and input signals must not be applied.
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 7. Semaphore Read After Write Timing (Either Side) [45, 46]
tSAA A0-A2 VALID ADRESS tAW SEM tSCE tSD IO0 tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE tDOE DATAIN VALID tPWE tHD DATAOUT VALID tHA tSOP VALID ADRESS tACE tOHA
Figure 8. Timing Diagram of Semaphore Contention [47, 48]
A0L-A2L
MATCH
R/WL SEML tSPS A0R-A2R MATCH
R/WR SEMR
Notes 45. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. 46. CE = HIGH for the duration of the above timing (both write and read cycle). 47. IO0R = IO0L = LOW (request semaphore); CER = CEL = HIGH. 48. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but the side that gets the semaphore cannot be predicted.
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 9. Timing Diagram of Read with BUSY (M/S = HIGH) [49]
tWC ADDRESSR R/WR MATCH tPWE
tSD DATA INR tPS ADDRESSL MATCH tBLA BUSYL tDDD DATAOUTL tWDD VALID
tHD
tBHA tBDD
VALID
Figure 10. Write Timing with Busy Input (M/S = LOW)
tPWE
R/W tWB
BUSY
tWH
Note 49. CEL = CER = LOW.
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 11. Busy Timing Diagram No.1 (CE Arbitration) CEL Valid First[50]
ADDRESSL,R CEL tPS CER tBLC BUSYR tBHC ADDRESS MATCH
CER Valid First
ADDRESSL,R CER tPS CEL tBLC BUSYL tBHC ADDRESS MATCH
Figure 12. Busy Timing Diagram No.2 (Address Arbitration) [50] Left Address Valid First
tRC or tWC ADDRESSL ADDRESS MATCH tPS ADDRESSR tBLA BUSYR tBHA ADDRESS MISMATCH
Right Address Valid First
tRC or tWC ADDRESSR ADDRESS MATCH tPS ADDRESSL tBLA BUSYL tBHA ADDRESS MISMATCH
Note 50. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY iS asserted.
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Switching Waveforms (continued)
Figure 13. Interrupt Timing Diagrams Left Side Sets INTR
ADDRESSL CEL R/WL INTR tINS [52] tWC WRITE 1FFF (OR 1/3FFF) tHA[51]
Right Side Clears INTR
ADDRESSR CER tINR [52] R/WR OER INTR
tRC READ 1FFF (OR 1/3FFF)
Right Side Sets INTL
tWC ADDRESSR CER R/WR INTL tINS
[52]
WRITE 1FFE (OR 1/3FFE) tHA[51]
Left Side Clears INTL
ADDRESSL CEL tINR[52] R/WL OEL INTL
Notes 51. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 52. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
tRC READ 1FFE OR 1/3FFE)
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Ordering Information
Table 7. 16K x16 1.8V Asynchronous Dual-Port SRAM Speed (ns) 55 55 Ordering Code CYDM256B16-55BVXC CYDM256B16-55BVXI Package Name BZ100 BZ100 Package Type 100-ball Pb-free 0.5 mm Pitch BGA 100-ball Pb-free 0.5 mm Pitch BGA Operating Range Commercial Industrial
Table 8. 8K x16 1.8V Asynchronous Dual-Port SRAM Speed (ns) 55 55 Ordering Code CYDM128B16-55BVXC CYDM128B16-55BVXI Package Name BZ100 BZ100 Package Type 100-ball Pb-free 0.5 mm Pitch BGA 100-ball Pb-free 0.5 mm Pitch BGA Operating Range Commercial Industrial
Table 9. 4K x16 1.8V Asynchronous Dual-Port SRAM Speed (ns) 55 55 Ordering Code CYDM064B16-55BVXC CYDM064B16-55BVXI Package Name BZ100 BZ100 Package Type 100-ball Pb-free 0.5 mm Pitch BGA 100-ball Pb-free 0.5 mm Pitch BGA Operating Range Commercial Industrial
Package Diagram
Figure 14. 100 VFBGA (6 x 6 x 1.0 mm) BZ100A
51-85209 *B
Document #: 001-00217 Rev. *F
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CYDM064B16, CYDM128B16, CYDM256B16
Document History Page
Document Title: CYDM064B16, CYDM128B16, CYDM256B16 1.8V 4K/8K/16K x 16 and 8K/16K x 8 MoBL(R) Dual-Port Static RAM Document Number: 001-00217 REV. ** *A *B *C ECN NO. 369423 381721 396697 404777 Orig. of Change YDT YDT KGH KGH Submission Date New data sheet Updated 2.5V/3.0V ICC, ISB1, ISB2, ISB4 Updated VOL ODR to 0.2V Updated ISB2 and ISB4 typo to mA. Updated tINS and tINR for -55 to 31ns. Updated IOH and IOL values for the 1.8V, 2.5V and 3.0V parameters VOH and VOL Replaced -35 speed bin with -40 Updated Switching Characteristics for VCC = 2.5V and VCC = 3.0V Included note 35 Removed part numbers CYDM128B08 and CYDM064B08 Corrected typo for power supply description in page 4 (3.0V instead of 3.3V) Updated tDDD timing value to be consistent with tWDD 07/31/2008 Removed all details of -40ns parts. Updated data sheet template. Description of Change
*D *E *F
426637 733676 2545957
KGH HKH OGC/AESA
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(c) Cypress Semiconductor Corporation, 2005-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-00217 Rev. *F
Revised July 31, 2008
Page 24 of 24
MoBL is a registered trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
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